The disclosed invention is generally directed to metal-oxide-semiconductor (MOS) floating gate transistor structures, and is more particularly directed to a single or double level metal floating gate transistor structure which includes a metal programming gate and polysilicon access and floating gates, and also to a process for making such floating gate transistor.
Floating gate transistors are intended to retain either an "ON" or "OFF" state without any bias power to the circuit. Thus, floating gate transistors are utilized as non-volatile memory elements, whereby data is stored by appropriately programming floating gate transistors in the ON or OFF states. The respective states of the floating gate transistors are sensed by appropriate read circuitry. Floating gate IGFETs are discussed in Physics of Semiconductor Devices, Sze, John Wiley & Sons, pages 550-555, 1969.
A known floating gate structure includes a polysilicon floating gate and a polysilicon control/access gate which partially overlies and extends beyond the floating gate. The gates are separated by an "interpoly" oxide layer. Typically, the floating gate is formed with a first polysilicon layer process, while the control/access gate is formed with a second polysilicon layer process, which is also utilized to form any standard transistor gates (i.e., non-floating).
A consideration with the foregoing structure is that the interpoly oxide tends to be leaky, unless high temperature oxide processing is utilized. However, such high temperature oxide processing has been shown to degrade the quality of the tunnel oxide beneath the floating gate. Thus, a trade-off must be made between retention and endurance.
Another consideration with the foregoing structure is that the fabrication processing typically utilized provides for a standard gate oxide thickness which depends on the thickness required for the interpoly oxide. Utilization of more advanced processes for thinner gate oxide would present difficulties.
Another known structure is similar to the foregoing described structure, except that the functions of the gates are reversed. In other words, the first polysilicon layer gate is utilized as the control/access gate, while the second polysilicon layer gate is utilized as the floating gate. Such structure advantageously allows for formation of the tunnel oxide after formation of the interpoly oxide, thus allowing for formation of high quality interpoly oxide without damage to the tunnel oxide. Also, such structure allows for concurrent formation of the oxide beneath the floating gate (distinct from the tunnel oxide) and the interpoly oxide, thus providing for a consistent capacitive coupling between the control/access gate and the floating gate.
However, the capacitive coupling factor is reduced since the control/access gate cannot capacitively couple to the floating gate area that necessarily extends beyond the control/access gate in a second poly layer floating gate configuration. Also, due to the necessarily reduced narrow size of the control/access gate in the channel region, the control/access gate may have higher resistance which results in slower access time.
A further consideration with both of the foregoing known structures is that the control gate is also utilized as the access gate, which results in a loss of charge on the floating gate after repeated read operations and decreased retention of the floating gate structure. This configuration also causes the "read" states of the floating gate transistor to have different degrees of "on", instead of being "off" or "on". An accurate reference device is required to be able to read the different "on" states, which complicates design.